1. Field of Use
The present invention relates to board testing methods and more particularly to methods of testing boards which include one or more digital programmable logic arrays.
2. Prior Art
As systems become more complex, the printed circuit boards used to construct such systems have increased in terms of circuit density and complexity. To facilitate design, updating or changes in logic circuits, Programmable Logic Devices (PLDs) such as user Programmable Gate Arrays, Programmable Logic Arrays (PLAs) and Programmable Array Logic Devices (PALs) are being used quite extensively. From their origins as a way to collect random logic in a system into a single device, PLDs are taking on a larger and larger role, replacing not only MSI and SSI-type logic but also VLSI peripheral logic functions. PLDs are being used in control functions for cache, random access memory, local bus, interrupt, disks and local-area networks, and as input/output interfaces, timer-counters, and clock generators. This increased use has greatly added to the burden of testing boards which include a number of PLDs.
One efficient way of carrying out board testing is through the use of an in-circuit tester. This type of equipment is usually directed toward testing one board component or element at a time by connecting to etches on the board which directly or indirectly connect to the component to be tested. This connection is often achieved using a bed-of-nails fixture which connects the tester to board etches which might not be accessible via other connection means. When the test is conducted, parts of the board may be forced to assume states which are distinct from their normal operating states. This forcing process is termed overdriving.
In order to be able to carry out testing efficiently on boards containing PLDs, circuit elements are often added during design of boards for purposes of testability. As applied to in-circuit testing, the term "testability" usually refers to the process of preconditioning parts of the board, other than that part or parts intended next to be tested, to assume states which will allow a test to be conducted with a minimum of forcing or overdriving. Further, it has been found that when it is not possible to completely disable a PLD during such testing, it may oscillate when its outputs are overdriven thereby invalidating test results.
The added circuit elements have taken the form of pull-up resistors and etch which connect to spare input pins of these PLDs. In many cases, these elements are added after the logic design is nearly completed. Thus, close coordination is required between the logic designer and test engineer to minimize the number of extra elements such as pull-ups added to the design exclusively for testability purposes. This process can be exceedingly time consuming, tedious and require the expenditure of valuable design resources.
Even after such efforts to include this type of testability, it may not be possible in certain situations to completely test all parts of a board because of on going design revisions or changes requiring certain components to share common pull-up resistors. A shared testability element may result in the conflicting need to force a common point to one logic state for preconditioning of other parts of the board while simultaneously forcing it to the opposite logic state to test a particular part or parts of the board. Testing these parts as a group, to resolve this problem, may not be efficiently accomplished because of tester driver multiplexing or because the individuals normally assigned to write the in circuit tester programs for such boards typically have no need to understand how a particular PLD operates and hence have limited expertise in this area. In practice, automatic test generators are generally used to generate such tests.
Accordingly, it is a primary object of the present invention to provide a more reliable method of testing boards containing programmable logic devices.
It is a further object of the present invention to provide an arrangement which requires the introduction of a minimum amount of additional circuits to a board for enabling testing of an entire board notwithstanding the number and the location of such PLDs on such board.